`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/04/28 11:37:54
// Design Name: 
// Module Name: Top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Top
(
    //ddr4
    input           ddr4_diff_clk_n ,
    input           ddr4_diff_clk_p ,
    output          C0_DDR4_act_n   ,
    output [16:0]   C0_DDR4_adr     ,
    output [1:0]    C0_DDR4_ba      ,
    output [0:0]    C0_DDR4_bg      ,
    output [0:0]    C0_DDR4_ck_c    ,
    output [0:0]    C0_DDR4_ck_t    ,
    output [0:0]    C0_DDR4_cke     ,
    output [0:0]    C0_DDR4_cs_n    ,
    inout  [7:0]    C0_DDR4_dm_n    ,
    inout  [63:0]   C0_DDR4_dq      ,
    inout  [7:0]    C0_DDR4_dqs_c   ,
    inout  [7:0]    C0_DDR4_dqs_t   ,
    output [0:0]    C0_DDR4_odt     ,
    output          C0_DDR4_reset_n ,
    output          ddr4_done_led   ,
    //pcie
    input  [0:0]    pcie_diff_clk_n ,
    input  [0:0]    pcie_diff_clk_p ,
    input  [7:0]    pcie_mgt_rxn    ,
    input  [7:0]    pcie_mgt_rxp    ,
    output [7:0]    pcie_mgt_txn    ,
    output [7:0]    pcie_mgt_txp    ,
    input           pcie_resetn     ,
    output          pcie_done_led   ,
    //led&key
    output [2:0]    led_tri_o       ,
    input  [2:0]    key_tri_i

);


//wire define
wire   ui_clk               ;
wire   user_irq_en_o        ;     
wire   fdma_wirq            ;
wire   [7:0]  wbuf_sync_o   ;
wire   [7:0]  xdma_irq_req  ;
wire   [15:0] data_out      ;
wire          data_vaild    ;
wire   [255:0] ud_wdata      ;



assign ud_wdata = { data_out,data_out,      //ch1 IQ
                    data_out,data_out,      //ch2 IQ
                    data_out,data_out,      //ch3 IQ
                    data_out,data_out,      //ch4 IQ
                    data_out,data_out,      //ch5 IQ
                    data_out,data_out,      //ch6 IQ
                    data_out,data_out,      //ch7 IQ
                    data_out,data_out };    //ch8 IQ

bd_irq  u_bd_irq (
    .ui_clk                  ( ui_clk          ),
    .user_irq_en_o           ( user_irq_en_o   ),
    .fdma_wirq               ( fdma_wirq       ),
    .wbuf_sync_o             ( wbuf_sync_o     ),

    .xdma_irq_req            ( xdma_irq_req    ) 
);


system_wrapper system_wrapper_i
(
    //ddr4
    .ddr4_diff_clk_n    (ddr4_diff_clk_n),
    .ddr4_diff_clk_p    (ddr4_diff_clk_p),
    .C0_DDR4_act_n      (C0_DDR4_act_n  ),
    .C0_DDR4_adr        (C0_DDR4_adr    ),
    .C0_DDR4_ba         (C0_DDR4_ba     ),
    .C0_DDR4_bg         (C0_DDR4_bg     ),
    .C0_DDR4_ck_c       (C0_DDR4_ck_c   ),
    .C0_DDR4_ck_t       (C0_DDR4_ck_t   ),
    .C0_DDR4_cke        (C0_DDR4_cke    ),
    .C0_DDR4_cs_n       (C0_DDR4_cs_n   ),
    .C0_DDR4_dm_n       (C0_DDR4_dm_n   ),
    .C0_DDR4_dq         (C0_DDR4_dq     ),
    .C0_DDR4_dqs_c      (C0_DDR4_dqs_c  ),
    .C0_DDR4_dqs_t      (C0_DDR4_dqs_t  ),
    .C0_DDR4_odt        (C0_DDR4_odt    ),
    .C0_DDR4_reset_n    (C0_DDR4_reset_n),
    .ddr4_done_led      (ddr4_done_led  ),//led
    //pcie
    .pcie_diff_clk_n    (pcie_diff_clk_n),
    .pcie_diff_clk_p    (pcie_diff_clk_p),
    .pcie_mgt_rxn       (pcie_mgt_rxn   ),
    .pcie_mgt_rxp       (pcie_mgt_rxp   ),
    .pcie_mgt_txn       (pcie_mgt_txn   ),
    .pcie_mgt_txp       (pcie_mgt_txp   ),
    .pcie_resetn        (pcie_resetn    ),
    .pcie_done_led      (pcie_done_led  ),//led
    //data_sim
    .data_out           (data_out       ),
    .data_vaild         (data_vaild     ),
    //ddr4_ui_clk 300M
    .ui_clk             (ui_clk         ),
    //ui_xdma_irq
    .user_irq_en_o      (user_irq_en_o  ),
    .user_irq_req_i     (xdma_irq_req   ),
    //led&key
    .key_tri_i          (key_tri_i      ),
    .led_tri_o          (led_tri_o      ),
    //udbuff
    .ud_wclk            (ud_wclk        ),//100M
    .ud_wdata           (ud_wdata       ),
    .fdma_wirq          (fdma_wirq      ),
    .wbuf_sync_o        (wbuf_sync_o    )
);


    
endmodule
